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IEC 61523-1-ed.3.0
Delay and power calculation standards - Part 1: Integrated Circuit (IC) Open Library Architecture (OLA)
Translate name
STANDARD published on 11.10.2023
The information about the standard:
Designation standards: IEC 61523-1-ed.3.0
Publication date standards: 11.10.2023
SKU: NS-1155951
Approximate weight : 300 g (0.66 lbs)
Country: International technical standard
Category: Technical standards IEC
The category - similar standards:
Industrial automation systems in generalLanguages used in information technology
Annotation of standard text IEC 61523-1-ed.3.0 :
IEC 61523-1:2023 focuses on delay and power calculation for integrated circuit design with support for modeling logical behavior and signal integrity. The standard specifications covered in this document are as follows: - Description language for timing and power modeling, called the “delay calculation language” (DCL) - Software procedural interface (PI) for communications between EDA applications and compiled libraries of DCL descriptions - Standard file exchange format for parasitic information about the chip design: Standard Parasitic Exchange Format (SPEF) - Informative usage examples - Informative notes. This is an IEC/IEEE dual logo standard.
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