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IEC 62530-2-ed.2.0
SystemVerilog - Part 2: Universal Verification Methodology Language Reference Manual
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STANDARD published on 11.10.2023
The information about the standard:
Designation standards: IEC 62530-2-ed.2.0
Publication date standards: 11.10.2023
SKU: NS-1155966
The number of pages: 457
Approximate weight : 1402 g (3.09 lbs)
Country: International technical standard
Category: Technical standards IEC
The category - similar standards:
Industrial automation systems in generalLanguages used in information technology
Annotation of standard text IEC 62530-2-ed.2.0 :
IEC 62530-2:2023 establishes the Universal Verification Methodology (UVM), a set of application programming interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog, IEEE Std 1800™.1. This is an IEC/IEEE dual logo standard.
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