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IEC 62530-ed.3.0
SystemVerilog - Unified Hardware Design, Specification, and Verification Language
Translate name
STANDARD published on 26.7.2021
The information about the standard:
Designation standards: IEC 62530-ed.3.0
Publication date standards: 26.7.2021
SKU: NS-1030838
The number of pages: 1315
Approximate weight : 3976 g (8.77 lbs)
Country: International technical standard
Category: Technical standards IEC
The category - similar standards:
Industrial automation systems in generalLanguages used in information technology
Annotation of standard text IEC 62530-ed.3.0 :
IEC 62530:2021(E) provides the definition of the language syntax and semantics for the IEEE 1800™ SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages. This edition corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions. This publication has the status of a double logo IEEE/IEC standard.
