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IEEE/IEC 62530-2-2023
IEEE/IEC International Standard--SystemVerilog--Part 2: Universal Verification Methodology Language Reference Manual
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STANDARD published on 19.10.2023
The information about the standard:
Designation standards: IEEE/IEC 62530-2-2023
Publication date standards: 19.10.2023
SKU: NS-1155987
The number of pages: 461
Approximate weight : 1414 g (3.12 lbs)
Country: International technical standard
Category: Technical standards IEEE
Annotation of standard text IEEE/IEC 62530-2-2023 :
Adoption Standard - Active.
The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.
ISBN: 979-8-8557-0213-2, 979-8-8557-0214-9
Number of Pages: 461
Product Code: STD26542, STDPD26542
Keywords: agent, blocking, callback, class, component, consumer, driver, event, export, factory, function, generator, IEEE 1800.2™, member, method, monitor, non-blocking, phase, port, register, resource, sequence, sequencer, transaction-level modeling, verification methodology
Category: Design Automation
