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IEEE/IEC 62530-2011
SystemVerilog -- Unified Hardware Design, Specification, and Verification Language
Automatically translated name:
SystemVerilog Unified Hardware Design, Specification, and Verification Language
STANDARD published on 19.5.2011
The information about the standard:
Designation standards: IEEE/IEC 62530-2011
Publication date standards: 19.5.2011
SKU: NS-415157
The number of pages: 1294
Approximate weight : 3913 g (8.63 lbs)
Country: International technical standard
Category: Technical standards IEEE
Annotation of standard text IEEE/IEC 62530-2011 :
- Active.
This standard represents a merger of two previous standards: IEEE Std 1364™-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document.
ISBN: 978-0-7381-6607-0, 978-0-7381-6633-9
Number of Pages: 1294
Product Code: STD97095, STDPD97095
Keywords: assertions, design automation, design verification, hardware description language, HDL, HDVL, PLI, programming language interface, SystemVerilog, Verilog, VPI
Category: Aerospace
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