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Delay and power calculation standards -- Part 1: Integrated circuit delay and power calculation systems
WITHDRAWN published on 1.12.2002
Selected format:Design automation. Part 1: VHDL language reference manual
WITHDRAWN published on 1.8.2001
Selected format:Behavioural languages. Part 2: VHDL multilogic system for model interoperability
WITHDRAWN published on 1.7.2002
Selected format:Behavioural languages. Part 3-2: Mathematical operation in VHDL
WITHDRAWN published on 1.7.2002
Selected format:Behavioural languages. Part 3-3: Synthesis in VHDL
WITHDRAWN published on 1.7.2002
Selected format:Design automation. Part 1: Standard test language for all systems. Common abbreviated test language for all systems (C/ATLAS)
Standard published on 1.11.2001
Selected format:Electronic Design Interchange Format (EDIF). Version 3 0 0 (IEC 61690- 1:2000)
Standard published on 1.11.2001
Selected format:Electronic Design Interchange Format (EDIF). Part 2: Version 4 0 0 (IEC 61690-2:2000)
Standard published on 1.11.2001
Selected format:Electronic design automation libraries -- Part 1: Input/Output buffer information specifications (IBIS version 3.2)
WITHDRAWN published on 1.12.2002
Selected format:Function blocks (FB) for process control and electronic device description language (EDDL) - Part 2: Specification of FB concept
Standard published on 1.2.2019
Selected format:Latest update: 2026-07-29 (Number of items: 2 290 440)
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